Due to the rapid development of electronic technology, electronic products with multi-functions and high performances have been developed so as to satisfy the demand of high integration and miniaturization of semiconductor packaging and to improve the storage capacity and performance of the semiconductor package, in order to accommodate tendency of the miniaturization, large storage capacity and high speed of electronic products. In prior art, most of the semiconductor packages are fabricated by the Multi Chip Module (MCM) technology. Such packing technology allowing the size of the package to be reduced and the electric performance to be improved has thereby become a mainstream packaging technology having at least two semiconductor chips placed on a chip carrier of single package in the MCM package, wherein each semiconductor chip is placed in the carrier by stacking. Such stack-type chip package structure is disclosed in U.S. Pat. No. 6,798,049.
As shown in FIG. 1, a cross-sectional view showing a Cavity-Down Ball Grid Array (CDBGA) package as disclosed in U.S. Pat. No. 6,798,049 is characterized in that forming a hole 101 in a circuit board 10 having a circuit layer 11; forming the circuit layer 11 having an electrically connecting pads 11a and bond pads 11b formed thereon on at least one side of the circuit board 10; combing two stacked semiconductor chips 121 and 122 in the hole 101, wherein the stacked semiconductor chips 121 and 122 are electrically connected by a bounding layer 13 formed therebetween and the semiconductor chip 122 is electrically connected to the bond pad 11b of the circuit layer 11 by a connection mean 14 such as a gold wire; filling an encapsulant 15 in the hole 101 of the circuit board 10 to encapsulate the semiconductor chips 121 and 122 and the connection mean 14; forming an insulating layer 16 on the circuit board; forming a plurality of openings 16a on the insulating layer 16 for exposing the electrically connecting pads 11a; forming an electric element 17 such as a solder ball on each opening 16a of the insulating layer 16 so as to complete the packaging process.
For such aforementioned package, the stacked semiconductor chips 121 and 122 are electrically connected to the circuit layer 11 by wire bonding. Since the height of the package is increased by the height of the arc line of the wire bond type structure, the purpose of being slim and small is thus unable to achieve. Moreover, the semiconductor chips 121 and 122 are electrically connected by the bonding layer 13 in chip-level, that is to say, the stacking process of the semiconductor chips 121 and 122 must be done in a semiconductor factory (wafer foundry) before having the packaging process being done in a semiconductor package factory, thus the process as such is more complicated and the cost of fabrication is increased.
If electrical performance and performance of modularization are improved by stacking process, it is required to proceed such stacking for further improvement. As a result, the thickness of the package will be increased as well as the complexness of the circuit layer 11 and the amount of the bonding pad 11b of the circuit layer 11. However, in order to increase density of the circuits and the amount of bonding pads 11b in a limiting or fixed area for packaging, the circuit of the circuit board used to carry the semiconductor chips 121, 122 must be fine enough to achieve the demand for the thin and small packaging. However, to reduce the area of circuit board by the fine circuit has a limited effect; and to improve the electric performance and the performance of modularization by directly stacking the semiconductor chips 121 and 122 is unfavorable as it may not be able to expand continuously due to the limited amount of the stacked chips, thus the purpose of being slim and small is also unfeasible.
In this regard, to increase the chip density placed on a multi-layer circuit board and decrease the area occupied by the semiconductor chips on the multi-layer circuit board for reducing the size of the package to improve the storage capacity have become an important issue in the circuit board industry.